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1 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com description the issi IS66WV1M16EALL and is66/67wv1m16ebll are high - speed,16m bit static rams organized as 1m words by 16 bits. it is fabricated using issi s high performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high - performance and low power consumption devices. when cs1# is high (deselected) or when cs2 is low ( deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels . easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we#) controls both writing and reading of the memory. a data byte allows upper byte (ub#) and lower byte (lb#) access. the is66wv1m16 eall and is66/67wv1m16ebll are packaged in the jedec standard 48 - ball mini bga ( 6mm x 8mm ). the device is also available for die sales. ? high - speed access time : - 70ns ( IS66WV1M16EALL ) - 55ns ( is66/67wv1m16ebll ) ? cmos lower power operation ? single power supply ? vdd =1.7v~1.95v ( IS66WV1M16EALL ) ? vdd =2.5v~3.6v (is66/67wv1m16ebll ) ? three state outputs ? data control for upper and lower bytes ? lead - free available 16mb low voltage, ultra low power pseudo cmos static ram features integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilu re or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authoriz ed for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances preliminary information october 2014 functional block diagram copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and it s p roducts at any time without notice. issi assu mes no liability arising out of the application or use of any information, products or services described herein. customers a re advised to obtain the latest version of this device specificatio n before relying on any published information and before placing orders for products. i/o0 - i/o7 lower byte a0~a19 cs2 address decode logic i/o data circuit 1m x 16 dram memory array column i/o control logic i/o8 - i/o15 upper byte vdd gnd cs1# oe# we# l b# ub#
2 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com 48 - ball minibga (6mm x 8mm) ball assignment 1 2 3 4 5 6 a b c d e f g h lb# oe# a0 i/q8 ub# a3 i/q9 i/q10 a5 gnd i q11 a17 i/q14 i/q13 a14 i/q15 a19 a12 a18 a8 a9 a1 a2 cs2 a4 cs1# i/q0 a6 i/q1 i q2 a7 i/q3 vdd a15 i/q5 i/q6 a13 we# i/q7 a10 a11 nc vdd i q12 nc a16 i/q4 gnd notes : 1. tsop package option is under evaluation. symbol type description a0~a19 input address inputs i/q0~i/q15 input / output data inputs/outputs cs1#, cs2 input chip enable oe# inpu t output enable we# inpu t write enable ub# inpu t upper byte select lb# inpu t lower byte select vdd powe r supply power gnd powe r supply ground pin descriptions pin configurations
3 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com power up initialization is 66 wv 1 m 16 eall and is 66 / 67 wv 1 m 16 ebll include an on - chip v oltage sensor used to launch the p o w er - up initialization proces s . when vdd reaches a sta b le l e v el at or ab o v e the vdd (min) the d e vice will require 50 s to complete its self - initialization proces s . du r ing the initialization pe r iod, cs 1 # should remain high . when initialize - ation is complet e , the d e vice is ready f or no r mal ope r ation . truth table operating range (v dd ) range ambient temperature IS66WV1M16EALL (70ns) is66wv1m16ebll (55ns, 70ns) is66wv1m16ebll (55ns, 70ns) industrial C 40 c to +85 c 1.7v C 1.95v 2.5v C 3.6v C automotive , a1 C 40 c to +85 c C C 2.5v C 3.6v automotive , a2 C 40 c to +105 c C C 2.5v C 3.6v mode we# cs1# cs2 oe# lb# ub# i/o0 C i/o7 i/o8 C i/o15 vdd current not selected x x h x x l x x x x h x high - z high - z high - z high - z i sb1 ,i sb2 i sb1 ,i sb2 output disabled h h x l l l h h h h h x l x h x l h high - z high - z high - z high - z high - z high - z i cc i cc i cc read h h h l l l h h h l l l l h l h l l d out high - z d out high - z d out d out i cc i cc i cc write l l l l l l h h h x x x l h l h l l din high - z din high - z din din i cc i cc i cc 50 us vdd vdd ( min ) 0 v device initialization device for normal operation
4 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com absolute maximum ratings notes: stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol p arameter t est conditions v dd min. max. unit v oh output high v oltage i oh = - 1 ma 2.5 - 3.6v 2.2 v v ol output l ow v oltage i ol = 2.1 ma 2.5 - 3.6v 0.4 v v ih input high v oltage (1) 2.5 - 3.6v 2.2 v dd + 0.3 v v il input l ow v oltage (1) 2.5 - 3.6v C 0.2 0.6 v i li input leakage gnd v in v dd C 1 1 a i lo output leakage gnd v out v dd , outputs disa b led C 1 1 a dc electrical char a cteristics (o v er ope r ating range) vdd = 2.5 v - 3.6v (is66/67wv1m16ebll) notes: 1. v ill (min.) = C 2.0v ac (pulse width < 10ns). not 100% tested. v ihh (max.) = v dd + 2.0v ac (pulse width < 10ns). not 100% test dc electrical char a cteristics (o v er ope r ating range) vdd = 1.7 v - 1.95v(IS66WV1M16EALL ) symbol p arameter t est conditions v dd min. max . unit v oh output high v oltage i oh = - 0.1 ma 1.7 - 1.95v 1.4 v v ol output l o w v oltage i ol = 0.1 ma 1.7 - 1.95v 0.2 v v ih input high v oltage (1) 1.7 - 1.95v 1.4 v dd + 0.2 v v il input l o w v oltage (1) 1.7 - 1.95v C 0.2 0.4 v i li input leakage gnd v in v dd C 1 1 a i lo output leakage gnd v out v dd , outputs disa b led C 1 1 a notes: 1. v ill (min.) = C 1.0v ac (pulse width < 10ns). not 100% tested. v ihh (max.) = v dd + 1.0v ac (pulse width < 10ns). not 100% test symbol parameter value unit v term terminal voltage with respect to gnd - 0.2 to v dd + 0.3 v t bias temperature under bias - 40 to +85 c v dd vdd related to gnd - 0.2 to +3.8 v t stg storage temperature - 65 to +150 c p t power dissipation 1.0 w
5 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com symbol description conditions min max unit c in input capacitance v in = 0v - 8 pf c io input/output capacitance (dq) v out = 0v - 10 pf capacitance notes: 1 . t ested initially and after a n y design or process changes that m a y af f ect these pa r ameter s . a c test conditions a c test l o ads r1 vtm output 30 pf including jig and scope r2 figure 1 r1 vtm output 5 pf including jig and scope r2 figure 2 symbol 1.7v C 1.95v 2.5v C 3.6v r1 ( ?) 3070 1029 r2 ( ?) 3150 1728 v ref 0.9v 1.4v v tm 1.8v 2.8v parameter 1.7v C 1.95v ( unit ) 2.5v C 3.6v ( unit ) input pulse level 0.4v to v dd C 0.2v 0.4v to v dd C 0.3v input rise and fall time 5ns 5ns input and output timing and reference level v ref v ref output load see figures 1 and 2 see figures 1 and 2
6 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com 1.7 v - 1.95v p o wer supp l y char a cteristics (o v er ope r ating range) symbol parameter conditions device typ. max. 70ns unit i cc vdd dynamic operating supply current v dd = max.,i out =0ma, f= f max , all inputs = 0.4v or vdd C 0.2v com. ind. auto - - - 20 25 30 ma i cc1 operating supply current v dd =max.,cs1#=0.2v, we#= v dd C 0.2v, f=1 mhz com. ind. auto - - - 4 4 10 ma i sb1 ttl standby current ( ttl inputs ) v dd = max.,v in =v ih or v il , cs1# = v ih , cs2=v il , f=1 mhz com. ind. auto - - - 0.6 0.6 1 ma i sb2 cmos standby current ( cmos inputs ) v dd =max., cs1# > v dd C 0.2v, cs2 < 0.2v, v in > v dd C 0.2v or v in < 0.2v, f=0 com. ind. auto - - - 100 120 150 ua notes: 1 . at f = f max , address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change. 2.5 v - 3.6v p o wer supp l y char a cteristics (o v er ope r ating range) symbol parameter conditions device typ max 55ns unit i cc vdd dynamic operating supply current v dd = max.,i out =0ma, f= f max , all inputs = 0.4v or v dd C 0.3v com. ind. auto typ .(2) - - - 25 28 35 15 ma i cc1 operating supply current v dd =max.,cs1#=0.2v, we#= v dd C 0.2v, f=1 mhz com. ind. auto - - - 5 5 10 ma i sb1 ttl standby current ( ttl inputs ) v dd = max.,v in =v ih or v il , cs1# = v ih , cs2=v il , f=1 mhz com. ind. auto - - - 0.6 0.6 1 ma i sb2 cmos standby current ( cmos inputs ) v dd =max., cs1# > v dd C 0.2v, cs2 < 0.2v, v in > v dd C 0.2v or v in < 0.2v , f=0 com. ind. auto typ. (2) - - - 100 130 150 75 ua notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, ta = 25 oc , and not 100% tested.
7 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com read cycle switching characteristics (1) (o v er ope r ating range) symbol parameter - 55 - 70 unit notes min max min max t rc read cycle time 55 - 70 - ns t aa address acess time - 55 - 70 ns 1 t oha output hold time 10 - 10 - ns t acs1/acs2 cs1#/cs2 acess time - 55 - 70 ns t doe oe# access time - 25 - 35 ns 1 t hzoe oe# to high - z output - 20 - 25 ns 2 t lzoe oe# to low - z output 5 - 5 - ns 2 t csm maximum cs1#/cs2 pulse width - 15 - 15 us t hzcs1/hzcs2 cs1#/cs2 to high - z output 0 20 0 25 ns 2 t lzcs1/hzcs2 cs1#/cs2 to low - z output 10 - 10 - ns 2 t ba ub#/lb# acess time - 55 - 70 ns 1 t hzb ub#/lb# to high - z output 0 20 0 25 ns 2 t lzb ub#/lb# to low - z output 0 - 0 - ns 2 t cph cs1# high (cs2 low) time 5 - 5 - ns ac waveforms read cycle no. 1 (1) (address controlled, oe #= v il , we #=v ih , ub# or lb# = v il ) notes: 1. we# is high for a read cycle. notes : 1 . t est conditions and output loading are specified in the ac test conditions and ac test loads (figure 1) on page 5 . 2. t ested with the load in figure 2 . t r ansition is measured 100 mv from steady - state v oltag e . not 100% tested. cs 1 # cs 2 trc address dq 0 - 15 toha toha taa previous data valid data valid tcsm
8 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com read cycle no. 2 (1) (cs1#, cs2, oe# and ub#/lb# controlled) notes: 1. address is valid prior to or coincident with cs1# low (cs2 high) transition, and is valid after or coincident with cs1# hi gh (cs2 low) transition. oe # cs 1 # cs 2 ub #, lb # dout taa address trc toha tdoe tcsm tcsm tlzoe tace 1 / tace 2 tlzcs 1 / tlzcs 2 thzoe thzcs 1 / thzcs 2 thzb tlzb tba high - z data valid
9 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com write cycle switching characteristics (1) (o v er ope r ating range) symbol parameter - 55 - 70 unit notes min max min max t wc write cycle time 55 - 70 - ns t scs1/scs2 cs1#/cs2 to write end 45 - 60 - ns t csm maximum cs1#/cs2 pulse width - 15 - 15 us t aw address setup to write time 45 - 60 - ns t ha address hold to end of write 0 - 0 - ns t sa address setup time 0 - 0 - ns t pwb ub#/lb# valid to end of write 45 - 60 - ns t pwe we# pulse width 45 - 60 - ns t sd data setup time 25 - 30 - ns t hzwe ub#/lb# to high - z output 0 - 0 - ns 3 t lzwe ub#/lb# to low - z output - 20 - 30 ns 3 t cph cs1# high (cs2 low) time 5 - 5 - ns notes : 1 . t est conditions and output loading are specified in the ac test conditions and ac test loads (figure 1) on page 5 . 2. the internal write time is defined by the overlap of cs1#, ub#, lb# and we# low, cs2 high . all signals must be in valid states to initiate a write, but anyone can go inactive to terminate write. the data input setup and hold timing are referenced to the rising or falling edge of the signals that terminates the write. 3 . t ested with the load in figure 2 . t r ansition is measured 100 mv from steady - state v oltag e . not 100% tested. 4. t pwe > t hzwe + t sd when oe# is low. 5 . chip select active time (both cs1# low and cs2 high) must not be longer than tcms of 15 us.
10 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com ac waveforms write cycle no. 1 (1) (cs1# controlled, oe#= high or low) notes: 1. write address is valid prior to or coincident with cs1# low (cs2 high) transition, and is valid after or coincident with c s1# high (cs2 low) transition. write cycle no. 2 (we# controlled, oe#= high during write cycle) address cs 1 # cs 2 we # ub #, lb # dout din twc tcsm tha taw tpwe tpwb tsa thzwe tlzwe tsd thd data - in valid data undefined high - z twc tscs 1 tha tscs 2 taw tpwe tsa thzwe tlzwe high - z tsd thd data undefined data - in valid address cs 1 # cs 2 we # ub #, lb # dout din oe #
11 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com write cycle no. 3 (we# controlled, oe#= low during write cycle) write cycle no. 4 (ub# / lb# controlled, cs2 is high during write cycle) address cs 1 # cs 2 we # ub #, lb # dout din twc tscs 1 tha tscs 2 taw tpwe tpwb tsa thzwe tlzwe tsd thd data - in valid data undefined high - z oe # low address cs 1 # we # dout din tcsm tsa thzwe tpwb tha data in valid address 1 address 2 twc twc tpwb data in valid data undefined thd tsd high - z tlzwe word 1 word 2 ub #, lb # tsa tha
12 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com avoidable timing and recommendations cs 1 # we # address cs 1 # we # address figure 3 a : tcsm violation figure 3 b : recommendation 15 us 5 ns 15 us 15 us
13 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com avoidable timing and recommendations notes: 1. psram uses dram cell which needs a refresh action pe r iodically to retain the in f o r mation . this refresh action is per f o r med only when the d e vice is not selected (chip select pins are disabled) . a hidden refresh action has to be ex ecuted b y the d e vice at least once e v e r y 15 s of tcsm . 2. figure 3a sh o ws a timing e xample in which consecuti v e read cycles for more than 15 us . this timing should be a v oided for proper refresh operation . refresh operation can begin only during chip select pins are disabled (cs1# is high and cs2 is low ) for more than 5ns. example on h o w to av oid tcsm violation in figure 3a is sh o wn in figure 3b. 3. figure 4a sh o ws a timing e xample in which a single write ope r ation is maintained f or a pe r iod g reater than 15 s . since a proper refresh action cannot be per f o r med du r ing device is selected by chip select pins, in f o r mation stored in the d e vice will not be retained if this timing occur s . figure 4b is a timing e xample of using cs1# signal toggling for proper the write ope r ation figure 4 b : recommendation we # , ub # , lb # address cs 1 # cs 1 #, we # ub # & lb # address figure 4 a : tcsm violation 15 us 15 us 15 us
14 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com config . speed (ns) order part no. package 1mx16 55 is66wv1m16ebll - 55bli mini bga(6mm x 8mm), lead - free 70 is66wv1m16ebll - 70bli mini bga(6mm x 8mm), lead - free notes : 1. please contact issi sram marketing at sram@issi.com if you need - 40 o c to +105 o c product. config . speed ( ns) order part no. package 1mx16 70 IS66WV1M16EALL - 70bli mini bga(6mm x 8mm), lead - free IS66WV1M16EALL industrial temperature range: ( - 40 o c to +85 o c ) voltage range : 1.7v to 1.95v is66wv1m16ebll industrial temperature range: ( - 40 o c to +85 o c ) voltage range : 2.5v to 3.6v is67wv1m16ebll automotive (a1) temperature range: ( - 40 o c to +85 o c ) voltage range : 2.5v to 3.6v config . speed (ns) order part no. package 1mx16 55 is67wv1m16ebll - 55bla1 mini bga(6mm x 8mm), lead - free 70 is67wv1m16ebll - 70bla1 mini bga(6mm x 8mm), lead - free
15 IS66WV1M16EALL is66/67wv1m16ebll rev. 0a | october 2014 www.issi.com - sram@issi.com

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